1. Field of the Invention
The present invention generally relates to fin-type field effect transistor (FinFET) structure and more particularly to an improved structure that includes differently sized spacers adjacent the fins which operate to change the effective width of the fins.
2. Description of the Related Art
As the end of linear scaling of planar complementary metal oxide semiconductors (CMOS) approaches, alternative device structures are being evaluated. One of the primary candidates is FinFET technology, where a thin fin, or pillar of silicon is created using sub-lithographic techniques, thereby allowing placement of the gate on sides of the Fin, which in the “on” state, fully depletes the silicon in the fin, making it a high performance device. U.S. Pat. No. 6,413,802 to Hu et al. (hereinafter “Hu”), which is incorporated herein by reference, discloses one example of a FinFET structure.
Conventional CMOS designers have the flexibility of using any (as limited by the design grid increments) width device, as well as gate lengths for a variety of performance and power characteristics. With FinFET technology, current integration techniques only allow for variation of the gate length but not the width (the width of a FinFET is determined by the height of the fin). This limitation in the device design creates difficulty for both porting existing designs into FinFET technology, as well as designing the plethora of circuits that designers have in their toolkit.
The current industry solution to circumvent this limitation has been to use multiple parallel fins controlled by the same gate. This quantizes the effective “width” of the device far more than the prior grid limitations. In addition, many designs incorporate “slightly larger than minimum” devices to get similar characteristics to the high performance device, without quite as much power consumption, or susceptibility to the effects of across chip line variation (ACLV). The quantization of 1 fin, 2 fins, 3 fins, etc., makes designing a “slightly larger than minimum” feature impossible. Additionally, for bulk FIN integration schemes, the methods for isolating the fins electrically from the substrate are fairly crude, and provide no means for creating multiple device widths.